(1) Field of the Invention
This invention relates to methods of forming buried contacts in MOSFET and CMOS devices and more particularly to methods to reduce the depth of the buried contact trench by using a thin polysilicon layer in a split polysilicon process.
(2) Description of the Related Art
The process of forming buried contacts results in the formation of a buried contact trench. The depth of this trench can become a problem for shallow junction devices. This invention describes a method of reducing the depth of this trench using a split polysilicon process.
U.S. Pat. No. 5,607,881 to Huang describes a method of forming buried contact junctions using over etching of a polysilicon layer to form a buried contact trench. An extra implant is implanted into the substrate around the trench. The buried contact connects to the source/drain regions through the extra implant around the trench.
U.S. Pat. No. 5,668,051 to Chen et al. describes a method of forming buried contacts having reduced series resistance. The buried contact trench is filled with doped polysilicon which reduces the series resistance between the buried contact and the source/drain regions.
U.S. Pat. No. 5,721,146 to Liaw et al. describes a method of forming a buried contact within a trench etched into the silicon substrate.
U.S. Pat. No. 5,258,096 to Sandhu et al. describes a method of using local etch stop layers for self aligned dry etching of contact vias with varying depths.
U.S. Pat. No. 4,679,171 to Logwood et al. describes a memory cell of four IGFET transistor cells arranged in rows and columns. The memory cells use split polysilicon word lines.
U.S. Pat. No. 5,134,085 to Gilgen et al. describes a 10-12 mask split polysilicon process for forming dynamic random access memories.
U.S. Pat. No. 5,578,873 to Manning describes a split polysilicon method for forming a contact electrode which connects to a buried contact region, but does not describe methods to reduce the depth of the buried contact trench.